Realization of Multiplexer Logic-Based 2-D Block FIR Filter Using Distributed Arithmetic

Ch. Pratyusha Chowdari; J. Beatrice Seventline

doi:10.24423/cames.538

Ch. Pratyusha Chowdari Gokaraju Rangaraju Institute of Engineering and Technology, Hyderabad, India
J. Beatrice Seventline GITAM University, Visakhapatnam, India

DOI: http://dx.doi.org/10.24423/cames.538

Abstract

This paper presents a novel systolic two-dimensional (2D) block finite impulse response (FIR) filter architecture using a distributed arithmetic (DA)-based multiplexer look-up table (DA-MUX-LUT). The proposed DA-MUX-LUT architecture computes the instantaneous partial-product using the bit vector. The switching-based LUT replaces memorybased structures and reduces hardware complexity. Block processing allows memory reuse, which reduces the number of registers to store the previous input samples. Parallel adders are substituted by a modified carry look-ahead adder (MCLA), which minimizes the delay. Moreover, a resource-sharing concept is introduced to the DA-MUX-LUT block that drastically reduces the adder requirement. The application specific integrated circuit (ASIC) synthesis results show that the proposed DA-MUX-LUT-based 2-D block FIR filter for filter size 8x8 and block size 4 has 31.22% less delay, 28.66% less area-delay product (ADP), 37.70% less power-delay product (PDP), and occupies almost the same area than the existing architecture.

Keywords

2-D FIR filter, switching-based LUT, distributed arithmetic, block processing,

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